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Key terms: tlb cpu cache address page entry miss memory translation os access hardware bits managed tlb entry physical software flushing change index valid rate task mips program handling tlb miss address space page table architecture perform instruction virtual address register option clock cycles tlb lookup managed tlb context switch if the cache exception cpu cache translation lookaside buffer operating system page fault cache access hardware tlb tlb management address translation flushing of the tlb Search external links cited by footnotes on Wikipedia page Translation lookaside buffer: |
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