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Key terms: layer link intel data clock each processors interconnect routing bits implementations rate use core if device flit receives link layer signal ghz architecture unit transfer sends gb need lanes physical transport layer message clock rate cache complex each direction hypertransport separate memory nehalem physical layer pair interface differential header payload intel's access data rate components more complex bus network transmitter one or more double xeon Search external links cited by footnotes on Wikipedia page Intel QuickPath Interconnect: |
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