Related articles:
Cycle stealing
IOMMU
Remote direct memory access
Programmed input/output
Southbridge (computing)
Blitter
Central processing unit
System-on-a-chip
CPU cache
Bus mastering
HyperTransport
Channel I/O
Larrabee (microarchitecture)
Cell (microprocessor)
IEEE 1284
Key terms:
dma
memory
transfer
cpu
controller
bus
device
address
cache
data
li
access
write
dma controller
direct
hardware
pci
register
read
processor
perform
direct memory access
dma channel
data transfer
request
mode
cycles
spe
component
coherent
disk
dma engine
system memory
memory address
peripheral
programmed
linux
pci bus
interface
input
initiate
isa
ibm
oat
slave
transfer data
arbiter
ownership
southbridge
cache coherency
read or write
address register
intel
interrupt
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