Related articles:
DDR3 SDRAM
SO-DIMM
DDR2 SDRAM
RDRAM
DDR SDRAM
Dynamic random access memory
Key terms:
dimm
mhz
data
sdram
memory
strobe
module
bits
mhz data
chips
accessed
dual
simms
bus
ranks
mhz clock for address
notch
memory module
clock for address and control
form factor
fit
registered
width
error
random
dynamic
data bits
sdram dimms
memory controller
ddr sdram
data bus
servers
achieved by clocking on both
voltage
detect
based on double data rate
clocking on both the rising
falling edge of the data
edge of the data strobes
ecc
frequencies
both the rising and falling
unbuffered
dimms based on double data
rate of the clock
rising and falling edge
double the rate
both sides
notch position
data path
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