|
Related articles:
DIMM
DDR3 SDRAM
SO-DIMM
DDR SDRAM
Dual-channel architecture
List of device bandwidths
Synchronous dynamic random access memory
Key terms: ddr data bus rate sdram memory modules clock dimms ecc latency bits mhz mt transfer twice jedec bandwidth chips cas notch clock rate data bus cycle bus clock byte additional data rate operating signal errors memory clock ddr sdram frequency whereas registered bits deep ddr dimms specification unbuffered compatible memory modules fully buffered designation memory cells transfer rate higher performance double data rate identified by an additional external data bus clock rate Search external links cited by footnotes on Wikipedia page DDR2 SDRAM: |
|