Related articles:
DDR3 SDRAM
DDR SDRAM
Double data rate
DIMM
SO-DIMM
Synchronous dynamic random-access memory
CAS latency
Dual-channel architecture
Fully Buffered DIMM
Memory timings
Prefetch buffer
Key terms:
sdram
modules
ddr
memory
rate
data
clock
bus
latency
dimms
transfer
performance
higher
clock rate
additional
bandwidth
mhz
buffered
jedec
bits
ecc
compatible
operating
ddr sdram
identified
data rate
data bus
chips
notch
signal
double
twice
frequency
bus clock rate
specification
backward compatible
memory modules
identified by an additional
registered
mt
higher performance
designation
require
fully buffered
double data rate
clock signal
memory cells
errors
transfer rate
memory clock
byte
internal clock
cas
maximum
prefetch
whereas
Search external links cited by footnotes on Wikipedia page DDR2 SDRAM:
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