Related articles:
Cache
Cache algorithms
Athlon
Phenom II
Pentium II
Intel 80486
Intel 80386
Translation lookaside buffer
Pentium
Harvard architecture
Hyper-threading
Memory management unit
Static random access memory
MIPS architecture
Von Neumann architecture
X86
Xeon
Computer
Central processing unit
Instruction pipeline
Processor register
Key terms:
cache
kib
tlb
associative
data cache
virtual address
sram
cache miss
cpu cache
mmu
cache hit
trace cache
cache entry
predictors
cache size
instruction cache
conflict misses
virtual aliases
associative cache
virtually indexed
set associative
cache memory
direct mapped
secondary cache
victim cache
page coloring
fully associative
compulsory misses
instruction fetch
hash function
memory accesses
high associativity
capacity miss rate
virtual address space
instruction and data caches
translation lookaside buffer
set associative cache
virtual hints
physically indexed
exclusive caches
cache index
virtual memory pages
cache hierarchy
fewer bits
cache algorithms
lru
indexed caches
kib pages
virtual indexing
best tradeoff
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