Related articles:
Cache
Athlon
Cache algorithms
Phenom II
Pentium II
Intel 80386
Pentium
Harvard architecture
Translation lookaside buffer
Hyper-threading
Simultaneous multithreading
Processor register
Memory management unit
Static random access memory
Instruction pipeline
MIPS architecture
Von Neumann architecture
X86
Xeon
Computer
Central processing unit
Key terms:
cache
kib
tlb
fetch
associative
sram
data cache
virtual address
cache miss
mmu
cpu cache
cache size
trace cache
lru
coherency
cache entry
predictors
associative cache
conflict misses
virtual aliases
instruction cache
secondary cache
virtually indexed
set associative
victim cache
data fetch
memory accesses
virtual hints
direct mapped
page coloring
kib pages
fewer bits
fully associative
compulsory misses
instruction fetch
physically indexed
cache index
branch prediction
best tradeoff
capacity miss rate
high associativity
cache hierarchy
virtual address space
exclusive caches
cache algorithms
virtual indexing
virtual memory pages
instruction and data caches
translation lookaside buffer
set associative cache
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